OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 81

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7517d 20h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7578d 17h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7578d 18h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7581d 01h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7613d 21h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7614d 20h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7634d 21h /dbg_interface/tags/rel_19/rtl/
61 Lapsus fixed. simons 7662d 21h /dbg_interface/tags/rel_19/rtl/
59 Reset value for riscsel register set to 1. simons 7662d 21h /dbg_interface/tags/rel_19/rtl/
57 Multiple cpu support added. simons 7662d 22h /dbg_interface/tags/rel_19/rtl/
53 Trst active high. Inverted on higher layer. mohor 7929d 20h /dbg_interface/tags/rel_19/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7929d 20h /dbg_interface/tags/rel_19/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7957d 08h /dbg_interface/tags/rel_19/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8112d 20h /dbg_interface/tags/rel_19/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8121d 02h /dbg_interface/tags/rel_19/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8127d 22h /dbg_interface/tags/rel_19/rtl/
44 Signal names changed to lower case. mohor 8127d 22h /dbg_interface/tags/rel_19/rtl/
43 Intentional error removed. mohor 8132d 21h /dbg_interface/tags/rel_19/rtl/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8132d 23h /dbg_interface/tags/rel_19/rtl/
41 Function changed to logic because of some synthesis warnings. mohor 8140d 20h /dbg_interface/tags/rel_19/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.