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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 91

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Rev Log message Author Age Path
91 tmp version. mohor 7471d 19h /dbg_interface/tags/rel_19/rtl/
90 tmp version. mohor 7472d 14h /dbg_interface/tags/rel_19/rtl/
89 temp4 version. mohor 7473d 20h /dbg_interface/tags/rel_19/rtl/
88 temp3 version. mohor 7474d 15h /dbg_interface/tags/rel_19/rtl/
87 tmp2 version. mohor 7475d 19h /dbg_interface/tags/rel_19/rtl/
86 Tmp version. mohor 7488d 15h /dbg_interface/tags/rel_19/rtl/
83 Small fix. mohor 7488d 16h /dbg_interface/tags/rel_19/rtl/
82 New directory structure. New version of the debug interface. mohor 7488d 17h /dbg_interface/tags/rel_19/rtl/
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7488d 17h /dbg_interface/tags/rel_19/rtl/
77 MBIST chain connection fixed. mohor 7549d 14h /dbg_interface/tags/rel_19/rtl/
73 CRC logic changed. mohor 7549d 15h /dbg_interface/tags/rel_19/rtl/
71 Mbist support added. simons 7551d 22h /dbg_interface/tags/rel_19/rtl/
67 Lower two address lines must be always zero. simons 7584d 18h /dbg_interface/tags/rel_19/rtl/
65 WB_CNTL register added, some syncronization fixes. simons 7585d 17h /dbg_interface/tags/rel_19/rtl/
63 Three more chains added for cpu debug access. simons 7605d 18h /dbg_interface/tags/rel_19/rtl/
61 Lapsus fixed. simons 7633d 18h /dbg_interface/tags/rel_19/rtl/
59 Reset value for riscsel register set to 1. simons 7633d 18h /dbg_interface/tags/rel_19/rtl/
57 Multiple cpu support added. simons 7633d 19h /dbg_interface/tags/rel_19/rtl/
53 Trst active high. Inverted on higher layer. mohor 7900d 17h /dbg_interface/tags/rel_19/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7900d 17h /dbg_interface/tags/rel_19/rtl/

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