URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 94

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Rev	Log message	Author	Age	Path
94	temp version. Resets will be changed in next version.	mohor	7466d 19h	/dbg_interface/tags/rel_19/rtl/
93	tmp version.	mohor	7467d 20h	/dbg_interface/tags/rel_19/rtl/
92	temp version.	mohor	7470d 23h	/dbg_interface/tags/rel_19/rtl/
91	tmp version.	mohor	7471d 18h	/dbg_interface/tags/rel_19/rtl/
90	tmp version.	mohor	7472d 13h	/dbg_interface/tags/rel_19/rtl/
89	temp4 version.	mohor	7473d 19h	/dbg_interface/tags/rel_19/rtl/
88	temp3 version.	mohor	7474d 14h	/dbg_interface/tags/rel_19/rtl/
87	tmp2 version.	mohor	7475d 19h	/dbg_interface/tags/rel_19/rtl/
86	Tmp version.	mohor	7488d 15h	/dbg_interface/tags/rel_19/rtl/
83	Small fix.	mohor	7488d 16h	/dbg_interface/tags/rel_19/rtl/
82	New directory structure. New version of the debug interface.	mohor	7488d 16h	/dbg_interface/tags/rel_19/rtl/
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7488d 16h	/dbg_interface/tags/rel_19/rtl/
77	MBIST chain connection fixed.	mohor	7549d 13h	/dbg_interface/tags/rel_19/rtl/
73	CRC logic changed.	mohor	7549d 15h	/dbg_interface/tags/rel_19/rtl/
71	Mbist support added.	simons	7551d 21h	/dbg_interface/tags/rel_19/rtl/
67	Lower two address lines must be always zero.	simons	7584d 17h	/dbg_interface/tags/rel_19/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7585d 16h	/dbg_interface/tags/rel_19/rtl/
63	Three more chains added for cpu debug access.	simons	7605d 17h	/dbg_interface/tags/rel_19/rtl/
61	Lapsus fixed.	simons	7633d 17h	/dbg_interface/tags/rel_19/rtl/
59	Reset value for riscsel register set to 1.	simons	7633d 17h	/dbg_interface/tags/rel_19/rtl/

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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] - Rev 94

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