OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 25

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 trst signal is synchronized to wb_clk_i. mohor 8259d 06h /dbg_interface/tags/rel_19/rtl/verilog/
23 Trace disabled by default. mohor 8266d 10h /dbg_interface/tags/rel_19/rtl/verilog/
22 Register length fixed. mohor 8266d 10h /dbg_interface/tags/rel_19/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8267d 06h /dbg_interface/tags/rel_19/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8268d 08h /dbg_interface/tags/rel_19/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8280d 09h /dbg_interface/tags/rel_19/rtl/verilog/
18 Reset signals are not combined any more. mohor 8282d 18h /dbg_interface/tags/rel_19/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 08h /dbg_interface/tags/rel_19/rtl/verilog/
15 bs_chain_o added. mohor 8308d 09h /dbg_interface/tags/rel_19/rtl/verilog/
13 Signal names changed to lowercase. mohor 8309d 09h /dbg_interface/tags/rel_19/rtl/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8310d 09h /dbg_interface/tags/rel_19/rtl/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8331d 05h /dbg_interface/tags/rel_19/rtl/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8335d 09h /dbg_interface/tags/rel_19/rtl/verilog/
8 Asynchronous set/reset not used in trace any more. mohor 8336d 07h /dbg_interface/tags/rel_19/rtl/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8337d 05h /dbg_interface/tags/rel_19/rtl/verilog/
2 Initial official release. mohor 8342d 05h /dbg_interface/tags/rel_19/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.