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[/] [dbg_interface/] [tags/] [rel_21/] - Rev 131

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Rev Log message Author Age Path
131 Documentation updated. Many missing things added. igorm 7420d 03h /dbg_interface/tags/rel_21/
129 New documentation. mohor 7462d 02h /dbg_interface/tags/rel_21/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7464d 09h /dbg_interface/tags/rel_21/
126 run_sim.scr renamed to run_sim for VATS. mohor 7467d 09h /dbg_interface/tags/rel_21/
124 Display for VATS added. mohor 7469d 06h /dbg_interface/tags/rel_21/
123 All flipflops are reset. mohor 7469d 06h /dbg_interface/tags/rel_21/
121 Port signals are all set to zero after reset. mohor 7472d 06h /dbg_interface/tags/rel_21/
120 test stall_test added. mohor 7472d 09h /dbg_interface/tags/rel_21/
119 cpu_stall_o activated as soon as bp occurs. mohor 7472d 09h /dbg_interface/tags/rel_21/
117 Define name changed. mohor 7474d 05h /dbg_interface/tags/rel_21/
116 Data latching changed when testing WB. mohor 7474d 06h /dbg_interface/tags/rel_21/
115 More debug data added. mohor 7474d 09h /dbg_interface/tags/rel_21/
114 CRC generation iand verification in bench changed. mohor 7474d 11h /dbg_interface/tags/rel_21/
113 IDCODE test improved. mohor 7474d 12h /dbg_interface/tags/rel_21/
112 dbg_tb_defines.v not used. mohor 7475d 06h /dbg_interface/tags/rel_21/
111 Define tap_defines.v added to test bench. mohor 7475d 06h /dbg_interface/tags/rel_21/
110 Waiting for "ready" improved. mohor 7475d 07h /dbg_interface/tags/rel_21/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7475d 12h /dbg_interface/tags/rel_21/
106 Sensitivity list updated. simons 7476d 10h /dbg_interface/tags/rel_21/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7477d 01h /dbg_interface/tags/rel_21/

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