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[/] [dbg_interface/] [tags/] [rel_21/] - Rev 34

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Rev Log message Author Age Path
34 Product brief added to cvs. mohor 8172d 11h /dbg_interface/tags/rel_21/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8177d 16h /dbg_interface/tags/rel_21/
32 Stupid bug that was entered by previous update fixed. mohor 8178d 15h /dbg_interface/tags/rel_21/
31 trst synchronization is not needed and was removed. mohor 8178d 15h /dbg_interface/tags/rel_21/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8189d 20h /dbg_interface/tags/rel_21/
29 Document revised and put tp better form. mohor 8193d 09h /dbg_interface/tags/rel_21/
28 TDO and TDO Enable signal are separated into two signals. mohor 8225d 17h /dbg_interface/tags/rel_21/
27 Warnings from synthesys tools fixed. mohor 8239d 18h /dbg_interface/tags/rel_21/
26 Warnings from synthesys tools fixed. mohor 8239d 18h /dbg_interface/tags/rel_21/
25 trst signal is synchronized to wb_clk_i. mohor 8240d 15h /dbg_interface/tags/rel_21/
24 CRC changed so more thorough testing is done. mohor 8241d 16h /dbg_interface/tags/rel_21/
23 Trace disabled by default. mohor 8247d 18h /dbg_interface/tags/rel_21/
22 Register length fixed. mohor 8247d 18h /dbg_interface/tags/rel_21/
21 CRC is returned when chain selection data is transmitted. mohor 8248d 14h /dbg_interface/tags/rel_21/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8249d 17h /dbg_interface/tags/rel_21/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8261d 18h /dbg_interface/tags/rel_21/
18 Reset signals are not combined any more. mohor 8264d 03h /dbg_interface/tags/rel_21/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8287d 16h /dbg_interface/tags/rel_21/
16 bs_chain_o port added. mohor 8289d 16h /dbg_interface/tags/rel_21/
15 bs_chain_o added. mohor 8289d 17h /dbg_interface/tags/rel_21/

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