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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 95

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Rev Log message Author Age Path
95 Temp version. mohor 7463d 16h /dbg_interface/tags/rel_21/bench/
93 tmp version. mohor 7465d 03h /dbg_interface/tags/rel_21/bench/
92 temp version. mohor 7468d 07h /dbg_interface/tags/rel_21/bench/
91 tmp version. mohor 7469d 02h /dbg_interface/tags/rel_21/bench/
90 tmp version. mohor 7469d 21h /dbg_interface/tags/rel_21/bench/
89 temp4 version. mohor 7471d 03h /dbg_interface/tags/rel_21/bench/
88 temp3 version. mohor 7471d 22h /dbg_interface/tags/rel_21/bench/
87 tmp2 version. mohor 7473d 03h /dbg_interface/tags/rel_21/bench/
80 New version of the debug interface. Not finished, yet. mohor 7486d 01h /dbg_interface/tags/rel_21/bench/
75 Simulation files. mohor 7546d 22h /dbg_interface/tags/rel_21/bench/
73 CRC logic changed. mohor 7546d 23h /dbg_interface/tags/rel_21/bench/
63 Three more chains added for cpu debug access. simons 7603d 01h /dbg_interface/tags/rel_21/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8081d 00h /dbg_interface/tags/rel_21/bench/
38 Few outputs for boundary scan chain added. mohor 8137d 00h /dbg_interface/tags/rel_21/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8140d 23h /dbg_interface/tags/rel_21/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8281d 03h /dbg_interface/tags/rel_21/bench/
15 bs_chain_o added. mohor 8283d 04h /dbg_interface/tags/rel_21/bench/
13 Signal names changed to lowercase. mohor 8284d 05h /dbg_interface/tags/rel_21/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8285d 05h /dbg_interface/tags/rel_21/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8306d 01h /dbg_interface/tags/rel_21/bench/

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