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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 111

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Rev Log message Author Age Path
111 Define tap_defines.v added to test bench. mohor 7462d 01h /dbg_interface/tags/rel_21/bench/verilog/
110 Waiting for "ready" improved. mohor 7462d 01h /dbg_interface/tags/rel_21/bench/verilog/
102 New version. mohor 7463d 20h /dbg_interface/tags/rel_21/bench/verilog/
101 Almost finished. mohor 7463d 21h /dbg_interface/tags/rel_21/bench/verilog/
99 cpu registers added. mohor 7464d 23h /dbg_interface/tags/rel_21/bench/verilog/
96 Working. mohor 7466d 03h /dbg_interface/tags/rel_21/bench/verilog/
95 Temp version. mohor 7466d 15h /dbg_interface/tags/rel_21/bench/verilog/
93 tmp version. mohor 7468d 03h /dbg_interface/tags/rel_21/bench/verilog/
92 temp version. mohor 7471d 06h /dbg_interface/tags/rel_21/bench/verilog/
91 tmp version. mohor 7472d 01h /dbg_interface/tags/rel_21/bench/verilog/
90 tmp version. mohor 7472d 20h /dbg_interface/tags/rel_21/bench/verilog/
89 temp4 version. mohor 7474d 02h /dbg_interface/tags/rel_21/bench/verilog/
88 temp3 version. mohor 7474d 21h /dbg_interface/tags/rel_21/bench/verilog/
87 tmp2 version. mohor 7476d 02h /dbg_interface/tags/rel_21/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7489d 00h /dbg_interface/tags/rel_21/bench/verilog/
75 Simulation files. mohor 7549d 22h /dbg_interface/tags/rel_21/bench/verilog/
73 CRC logic changed. mohor 7549d 22h /dbg_interface/tags/rel_21/bench/verilog/
63 Three more chains added for cpu debug access. simons 7606d 00h /dbg_interface/tags/rel_21/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8083d 23h /dbg_interface/tags/rel_21/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8140d 00h /dbg_interface/tags/rel_21/bench/verilog/

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