URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 63

Rev	Log message	Author	Age	Path
63	Three more chains added for cpu debug access.	simons	7645d 07h	/dbg_interface/tags/rel_21/bench/verilog/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8123d 06h	/dbg_interface/tags/rel_21/bench/verilog/
38	Few outputs for boundary scan chain added.	mohor	8179d 06h	/dbg_interface/tags/rel_21/bench/verilog/
36	Structure changed. Hooks for jtag chain added.	mohor	8183d 05h	/dbg_interface/tags/rel_21/bench/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8323d 09h	/dbg_interface/tags/rel_21/bench/verilog/
15	bs_chain_o added.	mohor	8325d 10h	/dbg_interface/tags/rel_21/bench/verilog/
13	Signal names changed to lowercase.	mohor	8326d 11h	/dbg_interface/tags/rel_21/bench/verilog/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8327d 11h	/dbg_interface/tags/rel_21/bench/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8348d 07h	/dbg_interface/tags/rel_21/bench/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8352d 10h	/dbg_interface/tags/rel_21/bench/verilog/
6	Minor changes for simulation.	mohor	8353d 09h	/dbg_interface/tags/rel_21/bench/verilog/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8354d 06h	/dbg_interface/tags/rel_21/bench/verilog/
2	Initial official release.	mohor	8359d 07h	/dbg_interface/tags/rel_21/bench/verilog/