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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 92

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Rev Log message Author Age Path
92 temp version. mohor 7485d 21h /dbg_interface/tags/rel_21/bench/verilog/
91 tmp version. mohor 7486d 16h /dbg_interface/tags/rel_21/bench/verilog/
90 tmp version. mohor 7487d 11h /dbg_interface/tags/rel_21/bench/verilog/
89 temp4 version. mohor 7488d 17h /dbg_interface/tags/rel_21/bench/verilog/
88 temp3 version. mohor 7489d 12h /dbg_interface/tags/rel_21/bench/verilog/
87 tmp2 version. mohor 7490d 17h /dbg_interface/tags/rel_21/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7503d 15h /dbg_interface/tags/rel_21/bench/verilog/
75 Simulation files. mohor 7564d 13h /dbg_interface/tags/rel_21/bench/verilog/
73 CRC logic changed. mohor 7564d 13h /dbg_interface/tags/rel_21/bench/verilog/
63 Three more chains added for cpu debug access. simons 7620d 15h /dbg_interface/tags/rel_21/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8098d 15h /dbg_interface/tags/rel_21/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8154d 15h /dbg_interface/tags/rel_21/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8158d 14h /dbg_interface/tags/rel_21/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8298d 18h /dbg_interface/tags/rel_21/bench/verilog/
15 bs_chain_o added. mohor 8300d 19h /dbg_interface/tags/rel_21/bench/verilog/
13 Signal names changed to lowercase. mohor 8301d 19h /dbg_interface/tags/rel_21/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8302d 19h /dbg_interface/tags/rel_21/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8323d 15h /dbg_interface/tags/rel_21/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8327d 19h /dbg_interface/tags/rel_21/bench/verilog/
6 Minor changes for simulation. mohor 8328d 17h /dbg_interface/tags/rel_21/bench/verilog/

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