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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 96

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Rev Log message Author Age Path
96 Working. mohor 7466d 09h /dbg_interface/tags/rel_21/bench/verilog/
95 Temp version. mohor 7466d 21h /dbg_interface/tags/rel_21/bench/verilog/
93 tmp version. mohor 7468d 08h /dbg_interface/tags/rel_21/bench/verilog/
92 temp version. mohor 7471d 12h /dbg_interface/tags/rel_21/bench/verilog/
91 tmp version. mohor 7472d 07h /dbg_interface/tags/rel_21/bench/verilog/
90 tmp version. mohor 7473d 02h /dbg_interface/tags/rel_21/bench/verilog/
89 temp4 version. mohor 7474d 08h /dbg_interface/tags/rel_21/bench/verilog/
88 temp3 version. mohor 7475d 02h /dbg_interface/tags/rel_21/bench/verilog/
87 tmp2 version. mohor 7476d 07h /dbg_interface/tags/rel_21/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7489d 05h /dbg_interface/tags/rel_21/bench/verilog/
75 Simulation files. mohor 7550d 03h /dbg_interface/tags/rel_21/bench/verilog/
73 CRC logic changed. mohor 7550d 03h /dbg_interface/tags/rel_21/bench/verilog/
63 Three more chains added for cpu debug access. simons 7606d 06h /dbg_interface/tags/rel_21/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8084d 05h /dbg_interface/tags/rel_21/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8140d 05h /dbg_interface/tags/rel_21/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8144d 04h /dbg_interface/tags/rel_21/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8284d 08h /dbg_interface/tags/rel_21/bench/verilog/
15 bs_chain_o added. mohor 8286d 09h /dbg_interface/tags/rel_21/bench/verilog/
13 Signal names changed to lowercase. mohor 8287d 09h /dbg_interface/tags/rel_21/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8288d 10h /dbg_interface/tags/rel_21/bench/verilog/

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