URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] - Rev 94

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Rev	Log message	Author	Age	Path
94	temp version. Resets will be changed in next version.	mohor	7483d 16h	/dbg_interface/tags/rel_21/rtl/
93	tmp version.	mohor	7484d 17h	/dbg_interface/tags/rel_21/rtl/
92	temp version.	mohor	7487d 21h	/dbg_interface/tags/rel_21/rtl/
91	tmp version.	mohor	7488d 16h	/dbg_interface/tags/rel_21/rtl/
90	tmp version.	mohor	7489d 11h	/dbg_interface/tags/rel_21/rtl/
89	temp4 version.	mohor	7490d 17h	/dbg_interface/tags/rel_21/rtl/
88	temp3 version.	mohor	7491d 12h	/dbg_interface/tags/rel_21/rtl/
87	tmp2 version.	mohor	7492d 17h	/dbg_interface/tags/rel_21/rtl/
86	Tmp version.	mohor	7505d 13h	/dbg_interface/tags/rel_21/rtl/
83	Small fix.	mohor	7505d 14h	/dbg_interface/tags/rel_21/rtl/
82	New directory structure. New version of the debug interface.	mohor	7505d 14h	/dbg_interface/tags/rel_21/rtl/
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7505d 14h	/dbg_interface/tags/rel_21/rtl/
77	MBIST chain connection fixed.	mohor	7566d 11h	/dbg_interface/tags/rel_21/rtl/
73	CRC logic changed.	mohor	7566d 13h	/dbg_interface/tags/rel_21/rtl/
71	Mbist support added.	simons	7568d 19h	/dbg_interface/tags/rel_21/rtl/
67	Lower two address lines must be always zero.	simons	7601d 15h	/dbg_interface/tags/rel_21/rtl/
65	WB_CNTL register added, some syncronization fixes.	simons	7602d 14h	/dbg_interface/tags/rel_21/rtl/
63	Three more chains added for cpu debug access.	simons	7622d 15h	/dbg_interface/tags/rel_21/rtl/
61	Lapsus fixed.	simons	7650d 15h	/dbg_interface/tags/rel_21/rtl/
59	Reset value for riscsel register set to 1.	simons	7650d 15h	/dbg_interface/tags/rel_21/rtl/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] - Rev 94

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