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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7475d 12h /dbg_interface/tags/rel_21/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7475d 16h /dbg_interface/tags/rel_21/rtl/verilog/
117 Define name changed. mohor 7477d 11h /dbg_interface/tags/rel_21/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7478d 18h /dbg_interface/tags/rel_21/rtl/verilog/
106 Sensitivity list updated. simons 7479d 17h /dbg_interface/tags/rel_21/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7480d 07h /dbg_interface/tags/rel_21/rtl/verilog/
102 New version. mohor 7480d 08h /dbg_interface/tags/rel_21/rtl/verilog/
101 Almost finished. mohor 7480d 09h /dbg_interface/tags/rel_21/rtl/verilog/
100 *** empty log message *** mohor 7481d 11h /dbg_interface/tags/rel_21/rtl/verilog/
99 cpu registers added. mohor 7481d 11h /dbg_interface/tags/rel_21/rtl/verilog/
97 Working. mohor 7482d 14h /dbg_interface/tags/rel_21/rtl/verilog/
95 Temp version. mohor 7483d 03h /dbg_interface/tags/rel_21/rtl/verilog/
94 temp version. Resets will be changed in next version. mohor 7483d 13h /dbg_interface/tags/rel_21/rtl/verilog/
93 tmp version. mohor 7484d 14h /dbg_interface/tags/rel_21/rtl/verilog/
92 temp version. mohor 7487d 18h /dbg_interface/tags/rel_21/rtl/verilog/
91 tmp version. mohor 7488d 13h /dbg_interface/tags/rel_21/rtl/verilog/
90 tmp version. mohor 7489d 08h /dbg_interface/tags/rel_21/rtl/verilog/
89 temp4 version. mohor 7490d 14h /dbg_interface/tags/rel_21/rtl/verilog/
88 temp3 version. mohor 7491d 09h /dbg_interface/tags/rel_21/rtl/verilog/
87 tmp2 version. mohor 7492d 14h /dbg_interface/tags/rel_21/rtl/verilog/

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