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[/] [dbg_interface/] [tags/] [rel_22/] - Rev 28

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Rev Log message Author Age Path
28 TDO and TDO Enable signal are separated into two signals. mohor 8271d 01h /dbg_interface/tags/rel_22/
27 Warnings from synthesys tools fixed. mohor 8285d 03h /dbg_interface/tags/rel_22/
26 Warnings from synthesys tools fixed. mohor 8285d 03h /dbg_interface/tags/rel_22/
25 trst signal is synchronized to wb_clk_i. mohor 8285d 23h /dbg_interface/tags/rel_22/
24 CRC changed so more thorough testing is done. mohor 8287d 01h /dbg_interface/tags/rel_22/
23 Trace disabled by default. mohor 8293d 03h /dbg_interface/tags/rel_22/
22 Register length fixed. mohor 8293d 03h /dbg_interface/tags/rel_22/
21 CRC is returned when chain selection data is transmitted. mohor 8293d 23h /dbg_interface/tags/rel_22/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8295d 02h /dbg_interface/tags/rel_22/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8307d 03h /dbg_interface/tags/rel_22/
18 Reset signals are not combined any more. mohor 8309d 12h /dbg_interface/tags/rel_22/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8333d 01h /dbg_interface/tags/rel_22/
16 bs_chain_o port added. mohor 8335d 01h /dbg_interface/tags/rel_22/
15 bs_chain_o added. mohor 8335d 02h /dbg_interface/tags/rel_22/
14 Document updated. mohor 8336d 00h /dbg_interface/tags/rel_22/
13 Signal names changed to lowercase. mohor 8336d 03h /dbg_interface/tags/rel_22/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8337d 03h /dbg_interface/tags/rel_22/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8357d 23h /dbg_interface/tags/rel_22/
10 First official release 1.0. mohor 8362d 03h /dbg_interface/tags/rel_22/
9 Working version. Few bugs fixed, comments added. mohor 8362d 03h /dbg_interface/tags/rel_22/

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