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[/] [dbg_interface/] [tags/] [rel_22/] - Rev 30

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Rev Log message Author Age Path
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8206d 07h /dbg_interface/tags/rel_22/
29 Document revised and put tp better form. mohor 8209d 20h /dbg_interface/tags/rel_22/
28 TDO and TDO Enable signal are separated into two signals. mohor 8242d 04h /dbg_interface/tags/rel_22/
27 Warnings from synthesys tools fixed. mohor 8256d 05h /dbg_interface/tags/rel_22/
26 Warnings from synthesys tools fixed. mohor 8256d 05h /dbg_interface/tags/rel_22/
25 trst signal is synchronized to wb_clk_i. mohor 8257d 02h /dbg_interface/tags/rel_22/
24 CRC changed so more thorough testing is done. mohor 8258d 03h /dbg_interface/tags/rel_22/
23 Trace disabled by default. mohor 8264d 06h /dbg_interface/tags/rel_22/
22 Register length fixed. mohor 8264d 06h /dbg_interface/tags/rel_22/
21 CRC is returned when chain selection data is transmitted. mohor 8265d 02h /dbg_interface/tags/rel_22/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8266d 05h /dbg_interface/tags/rel_22/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8278d 05h /dbg_interface/tags/rel_22/
18 Reset signals are not combined any more. mohor 8280d 14h /dbg_interface/tags/rel_22/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8304d 04h /dbg_interface/tags/rel_22/
16 bs_chain_o port added. mohor 8306d 03h /dbg_interface/tags/rel_22/
15 bs_chain_o added. mohor 8306d 05h /dbg_interface/tags/rel_22/
14 Document updated. mohor 8307d 02h /dbg_interface/tags/rel_22/
13 Signal names changed to lowercase. mohor 8307d 05h /dbg_interface/tags/rel_22/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8308d 05h /dbg_interface/tags/rel_22/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8329d 01h /dbg_interface/tags/rel_22/

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