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[/] [dbg_interface/] [tags/] [rel_23/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5562d 13h /dbg_interface/tags/rel_23/rtl/verilog/
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7362d 19h /dbg_interface/tags/rel_23/rtl/verilog/
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7362d 19h /dbg_interface/tags/rel_23/rtl/verilog/
146 Changes for the FormalPRO. igorm 7366d 16h /dbg_interface/tags/rel_23/rtl/verilog/
144 Port names and defines for the supported CPUs changed. igorm 7366d 21h /dbg_interface/tags/rel_23/rtl/verilog/
143 Signals for easier debugging removed. igorm 7366d 23h /dbg_interface/tags/rel_23/rtl/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7367d 19h /dbg_interface/tags/rel_23/rtl/verilog/
139 New release of the debug interface (3rd. release). igorm 7370d 13h /dbg_interface/tags/rel_23/rtl/verilog/
138 Temp version before changing dbg interface. igorm 7376d 17h /dbg_interface/tags/rel_23/rtl/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7428d 23h /dbg_interface/tags/rel_23/rtl/verilog/
123 All flipflops are reset. mohor 7433d 19h /dbg_interface/tags/rel_23/rtl/verilog/
121 Port signals are all set to zero after reset. mohor 7436d 19h /dbg_interface/tags/rel_23/rtl/verilog/
119 cpu_stall_o activated as soon as bp occurs. mohor 7436d 23h /dbg_interface/tags/rel_23/rtl/verilog/
117 Define name changed. mohor 7438d 19h /dbg_interface/tags/rel_23/rtl/verilog/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7440d 02h /dbg_interface/tags/rel_23/rtl/verilog/
106 Sensitivity list updated. simons 7441d 00h /dbg_interface/tags/rel_23/rtl/verilog/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7441d 15h /dbg_interface/tags/rel_23/rtl/verilog/
102 New version. mohor 7441d 15h /dbg_interface/tags/rel_23/rtl/verilog/
101 Almost finished. mohor 7441d 16h /dbg_interface/tags/rel_23/rtl/verilog/
100 *** empty log message *** mohor 7442d 18h /dbg_interface/tags/rel_23/rtl/verilog/

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