URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_24/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5647d 03h	/dbg_interface/tags/rel_24/
151	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7445d 04h	/tags/rel_24/
150	Zero is shifted out when CTRL_READ command is active.	igorm	7445d 04h	/trunk/
147	CPU_WR_CTRL and CPU_RD_CTRL defines changed.	igorm	7447d 09h	/trunk/
146	Changes for the FormalPRO.	igorm	7451d 06h	/trunk/
145	Support for 2 CPUs added.	igorm	7451d 10h	/trunk/
144	Port names and defines for the supported CPUs changed.	igorm	7451d 11h	/trunk/
143	Signals for easier debugging removed.	igorm	7451d 13h	/trunk/
142	Typo fixed.	igorm	7451d 14h	/trunk/
141	data_cnt_lim length changed to reduce number of warnings.	igorm	7452d 09h	/trunk/
140	CRC checking of incoming CRC added to all tasks.	igorm	7453d 00h	/trunk/
139	New release of the debug interface (3rd. release).	igorm	7455d 03h	/trunk/
138	Temp version before changing dbg interface.	igorm	7461d 07h	/trunk/
136	Table describing chain codes added.	igorm	7465d 08h	/trunk/
135	'hz changed to 1'hz because Icarus complains.	igorm	7468d 07h	/trunk/
132	Documentation updated. Many missing things added.	igorm	7469d 06h	/trunk/
131	Documentation updated. Many missing things added.	igorm	7469d 06h	/trunk/
129	New documentation.	mohor	7511d 05h	/trunk/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7513d 13h	/trunk/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7516d 12h	/trunk/