URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] - Rev 17

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8281d 08h	/dbg_interface/tags/rel_6/
16	bs_chain_o port added.	mohor	8283d 08h	/dbg_interface/tags/rel_6/
15	bs_chain_o added.	mohor	8283d 09h	/dbg_interface/tags/rel_6/
14	Document updated.	mohor	8284d 07h	/dbg_interface/tags/rel_6/
13	Signal names changed to lowercase.	mohor	8284d 10h	/dbg_interface/tags/rel_6/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8285d 10h	/dbg_interface/tags/rel_6/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8306d 06h	/dbg_interface/tags/rel_6/
10	First official release 1.0.	mohor	8310d 10h	/dbg_interface/tags/rel_6/
9	Working version. Few bugs fixed, comments added.	mohor	8310d 10h	/dbg_interface/tags/rel_6/
8	Asynchronous set/reset not used in trace any more.	mohor	8311d 08h	/dbg_interface/tags/rel_6/
7	First official release 1.0.	mohor	8311d 08h	/dbg_interface/tags/rel_6/
6	Minor changes for simulation.	mohor	8311d 08h	/dbg_interface/tags/rel_6/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8312d 06h	/dbg_interface/tags/rel_6/
4	Initial official release.	mohor	8317d 06h	/dbg_interface/tags/rel_6/
2	Initial official release.	mohor	8317d 06h	/dbg_interface/tags/rel_6/
1	Standard project directories initialized by cvs2svn.		8317d 06h	/dbg_interface/tags/rel_6/