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[/] [dbg_interface/] [tags/] [rel_6/] - Rev 32

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Rev Log message Author Age Path
32 Stupid bug that was entered by previous update fixed. mohor 8186d 11h /dbg_interface/tags/rel_6/
31 trst synchronization is not needed and was removed. mohor 8186d 12h /dbg_interface/tags/rel_6/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8197d 16h /dbg_interface/tags/rel_6/
29 Document revised and put tp better form. mohor 8201d 05h /dbg_interface/tags/rel_6/
28 TDO and TDO Enable signal are separated into two signals. mohor 8233d 13h /dbg_interface/tags/rel_6/
27 Warnings from synthesys tools fixed. mohor 8247d 14h /dbg_interface/tags/rel_6/
26 Warnings from synthesys tools fixed. mohor 8247d 14h /dbg_interface/tags/rel_6/
25 trst signal is synchronized to wb_clk_i. mohor 8248d 11h /dbg_interface/tags/rel_6/
24 CRC changed so more thorough testing is done. mohor 8249d 13h /dbg_interface/tags/rel_6/
23 Trace disabled by default. mohor 8255d 15h /dbg_interface/tags/rel_6/
22 Register length fixed. mohor 8255d 15h /dbg_interface/tags/rel_6/
21 CRC is returned when chain selection data is transmitted. mohor 8256d 11h /dbg_interface/tags/rel_6/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8257d 14h /dbg_interface/tags/rel_6/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8269d 14h /dbg_interface/tags/rel_6/
18 Reset signals are not combined any more. mohor 8271d 23h /dbg_interface/tags/rel_6/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8295d 13h /dbg_interface/tags/rel_6/
16 bs_chain_o port added. mohor 8297d 13h /dbg_interface/tags/rel_6/
15 bs_chain_o added. mohor 8297d 14h /dbg_interface/tags/rel_6/
14 Document updated. mohor 8298d 11h /dbg_interface/tags/rel_6/
13 Signal names changed to lowercase. mohor 8298d 14h /dbg_interface/tags/rel_6/

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