OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] - Rev 36

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
36 Structure changed. Hooks for jtag chain added. mohor 8155d 08h /dbg_interface/tags/rel_6/
35 Dbg support datasheet added to cvs. mohor 8179d 13h /dbg_interface/tags/rel_6/
34 Product brief added to cvs. mohor 8180d 07h /dbg_interface/tags/rel_6/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8185d 11h /dbg_interface/tags/rel_6/
32 Stupid bug that was entered by previous update fixed. mohor 8186d 10h /dbg_interface/tags/rel_6/
31 trst synchronization is not needed and was removed. mohor 8186d 11h /dbg_interface/tags/rel_6/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8197d 16h /dbg_interface/tags/rel_6/
29 Document revised and put tp better form. mohor 8201d 04h /dbg_interface/tags/rel_6/
28 TDO and TDO Enable signal are separated into two signals. mohor 8233d 12h /dbg_interface/tags/rel_6/
27 Warnings from synthesys tools fixed. mohor 8247d 13h /dbg_interface/tags/rel_6/
26 Warnings from synthesys tools fixed. mohor 8247d 14h /dbg_interface/tags/rel_6/
25 trst signal is synchronized to wb_clk_i. mohor 8248d 10h /dbg_interface/tags/rel_6/
24 CRC changed so more thorough testing is done. mohor 8249d 12h /dbg_interface/tags/rel_6/
23 Trace disabled by default. mohor 8255d 14h /dbg_interface/tags/rel_6/
22 Register length fixed. mohor 8255d 14h /dbg_interface/tags/rel_6/
21 CRC is returned when chain selection data is transmitted. mohor 8256d 10h /dbg_interface/tags/rel_6/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8257d 13h /dbg_interface/tags/rel_6/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8269d 13h /dbg_interface/tags/rel_6/
18 Reset signals are not combined any more. mohor 8271d 22h /dbg_interface/tags/rel_6/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8295d 12h /dbg_interface/tags/rel_6/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.