OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [bench/] [verilog/] - Rev 12

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8299d 18h /dbg_interface/tags/rel_6/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8320d 14h /dbg_interface/tags/rel_6/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8324d 18h /dbg_interface/tags/rel_6/bench/verilog/
6 Minor changes for simulation. mohor 8325d 16h /dbg_interface/tags/rel_6/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8326d 14h /dbg_interface/tags/rel_6/bench/verilog/
2 Initial official release. mohor 8331d 14h /dbg_interface/tags/rel_6/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.