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[/] [dbg_interface/] [tags/] [rel_6/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5596d 04h /dbg_interface/tags/rel_6/bench/verilog/
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7617d 10h /dbg_interface/tags/rel_6/bench/verilog/
63 Three more chains added for cpu debug access. simons 7617d 10h /dbg_interface/tags/rel_6/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8095d 09h /dbg_interface/tags/rel_6/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8151d 09h /dbg_interface/tags/rel_6/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8155d 08h /dbg_interface/tags/rel_6/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8295d 12h /dbg_interface/tags/rel_6/bench/verilog/
15 bs_chain_o added. mohor 8297d 13h /dbg_interface/tags/rel_6/bench/verilog/
13 Signal names changed to lowercase. mohor 8298d 14h /dbg_interface/tags/rel_6/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8299d 14h /dbg_interface/tags/rel_6/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8320d 10h /dbg_interface/tags/rel_6/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8324d 13h /dbg_interface/tags/rel_6/bench/verilog/
6 Minor changes for simulation. mohor 8325d 12h /dbg_interface/tags/rel_6/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8326d 09h /dbg_interface/tags/rel_6/bench/verilog/
2 Initial official release. mohor 8331d 10h /dbg_interface/tags/rel_6/bench/verilog/

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