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[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 36

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Rev Log message Author Age Path
36 Structure changed. Hooks for jtag chain added. mohor 8196d 19h /dbg_interface/tags/rel_6/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8226d 22h /dbg_interface/tags/rel_6/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8227d 20h /dbg_interface/tags/rel_6/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8227d 21h /dbg_interface/tags/rel_6/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8239d 02h /dbg_interface/tags/rel_6/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8274d 23h /dbg_interface/tags/rel_6/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8289d 00h /dbg_interface/tags/rel_6/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8289d 00h /dbg_interface/tags/rel_6/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8289d 21h /dbg_interface/tags/rel_6/rtl/verilog/
23 Trace disabled by default. mohor 8297d 00h /dbg_interface/tags/rel_6/rtl/verilog/
22 Register length fixed. mohor 8297d 00h /dbg_interface/tags/rel_6/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8297d 20h /dbg_interface/tags/rel_6/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8298d 23h /dbg_interface/tags/rel_6/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8311d 00h /dbg_interface/tags/rel_6/rtl/verilog/
18 Reset signals are not combined any more. mohor 8313d 09h /dbg_interface/tags/rel_6/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8336d 22h /dbg_interface/tags/rel_6/rtl/verilog/
15 bs_chain_o added. mohor 8338d 23h /dbg_interface/tags/rel_6/rtl/verilog/
13 Signal names changed to lowercase. mohor 8340d 00h /dbg_interface/tags/rel_6/rtl/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8341d 00h /dbg_interface/tags/rel_6/rtl/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8361d 20h /dbg_interface/tags/rel_6/rtl/verilog/

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