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[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 51

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51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7933d 16h /dbg_interface/tags/rel_6/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 04h /dbg_interface/tags/rel_6/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8097d 10h /dbg_interface/tags/rel_6/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8104d 06h /dbg_interface/tags/rel_6/rtl/verilog/
44 Signal names changed to lower case. mohor 8104d 06h /dbg_interface/tags/rel_6/rtl/verilog/
43 Intentional error removed. mohor 8109d 06h /dbg_interface/tags/rel_6/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8109d 08h /dbg_interface/tags/rel_6/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8117d 05h /dbg_interface/tags/rel_6/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8131d 05h /dbg_interface/tags/rel_6/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8132d 06h /dbg_interface/tags/rel_6/rtl/verilog/
38 Few outputs for boundary scan chain added. mohor 8145d 05h /dbg_interface/tags/rel_6/rtl/verilog/
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8145d 09h /dbg_interface/tags/rel_6/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8149d 04h /dbg_interface/tags/rel_6/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8179d 07h /dbg_interface/tags/rel_6/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8180d 06h /dbg_interface/tags/rel_6/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8180d 06h /dbg_interface/tags/rel_6/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8191d 11h /dbg_interface/tags/rel_6/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8227d 08h /dbg_interface/tags/rel_6/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8241d 09h /dbg_interface/tags/rel_6/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8241d 09h /dbg_interface/tags/rel_6/rtl/verilog/

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