URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [sim/] [rtl_sim/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5581d 09h	/dbg_interface/tags/rel_6/sim/rtl_sim/
64	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7602d 15h	/dbg_interface/tags/rel_6/sim/rtl_sim/
36	Structure changed. Hooks for jtag chain added.	mohor	8140d 13h	/dbg_interface/tags/rel_6/sim/rtl_sim/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8280d 17h	/dbg_interface/tags/rel_6/sim/rtl_sim/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8311d 14h	/dbg_interface/tags/rel_6/sim/rtl_sim/
2	Initial official release.	mohor	8316d 15h	/dbg_interface/tags/rel_6/sim/rtl_sim/