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[/] [dbg_interface/] [tags/] [rel_7/] - Rev 158

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Rev Log message Author Age Path
158 root 5631d 09h /dbg_interface/tags/rel_7/
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7632d 14h /tags/rel_7/
65 WB_CNTL register added, some syncronization fixes. simons 7632d 14h /trunk/
63 Three more chains added for cpu debug access. simons 7652d 15h /trunk/
61 Lapsus fixed. simons 7680d 15h /trunk/
59 Reset value for riscsel register set to 1. simons 7680d 15h /trunk/
57 Multiple cpu support added. simons 7680d 16h /trunk/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7947d 13h /trunk/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7947d 13h /trunk/
53 Trst active high. Inverted on higher layer. mohor 7947d 14h /trunk/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7947d 14h /trunk/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7975d 02h /trunk/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7975d 03h /trunk/
47 mon_cntl_o signals that controls monitor mux added. mohor 8130d 14h /trunk/
46 Asynchronous reset used instead of synchronous. mohor 8138d 20h /trunk/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8145d 16h /trunk/
44 Signal names changed to lower case. mohor 8145d 16h /trunk/
43 Intentional error removed. mohor 8150d 15h /trunk/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8150d 17h /trunk/
41 Function changed to logic because of some synthesis warnings. mohor 8158d 14h /trunk/

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