URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_7/] [bench/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5561d 19h	/dbg_interface/tags/rel_7/bench/
66	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7563d 00h	/dbg_interface/tags/rel_7/bench/
63	Three more chains added for cpu debug access.	simons	7583d 01h	/dbg_interface/tags/rel_7/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8061d 00h	/dbg_interface/tags/rel_7/bench/
38	Few outputs for boundary scan chain added.	mohor	8117d 01h	/dbg_interface/tags/rel_7/bench/
36	Structure changed. Hooks for jtag chain added.	mohor	8121d 00h	/dbg_interface/tags/rel_7/bench/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8261d 03h	/dbg_interface/tags/rel_7/bench/
15	bs_chain_o added.	mohor	8263d 04h	/dbg_interface/tags/rel_7/bench/
13	Signal names changed to lowercase.	mohor	8264d 05h	/dbg_interface/tags/rel_7/bench/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8265d 05h	/dbg_interface/tags/rel_7/bench/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8286d 01h	/dbg_interface/tags/rel_7/bench/
9	Working version. Few bugs fixed, comments added.	mohor	8290d 05h	/dbg_interface/tags/rel_7/bench/
6	Minor changes for simulation.	mohor	8291d 03h	/dbg_interface/tags/rel_7/bench/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8292d 01h	/dbg_interface/tags/rel_7/bench/
2	Initial official release.	mohor	8297d 01h	/dbg_interface/tags/rel_7/bench/