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[/] [dbg_interface/] [tags/] [rel_7/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5582d 14h /dbg_interface/tags/rel_7/bench/verilog/
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7583d 20h /dbg_interface/tags/rel_7/bench/verilog/
63 Three more chains added for cpu debug access. simons 7603d 20h /dbg_interface/tags/rel_7/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8081d 19h /dbg_interface/tags/rel_7/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8137d 20h /dbg_interface/tags/rel_7/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8141d 19h /dbg_interface/tags/rel_7/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8281d 23h /dbg_interface/tags/rel_7/bench/verilog/
15 bs_chain_o added. mohor 8284d 00h /dbg_interface/tags/rel_7/bench/verilog/
13 Signal names changed to lowercase. mohor 8285d 00h /dbg_interface/tags/rel_7/bench/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8286d 00h /dbg_interface/tags/rel_7/bench/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8306d 20h /dbg_interface/tags/rel_7/bench/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8311d 00h /dbg_interface/tags/rel_7/bench/verilog/
6 Minor changes for simulation. mohor 8311d 22h /dbg_interface/tags/rel_7/bench/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8312d 20h /dbg_interface/tags/rel_7/bench/verilog/
2 Initial official release. mohor 8317d 20h /dbg_interface/tags/rel_7/bench/verilog/

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