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[/] [dbg_interface/] [tags/] [rel_7/] [sim/] [rtl_sim/] - Rev 66

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66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7605d 03h /dbg_interface/tags/rel_7/sim/rtl_sim/
36 Structure changed. Hooks for jtag chain added. mohor 8163d 02h /dbg_interface/tags/rel_7/sim/rtl_sim/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8303d 06h /dbg_interface/tags/rel_7/sim/rtl_sim/
5 Trace fixed. Some registers changed, trace simplified. mohor 8334d 03h /dbg_interface/tags/rel_7/sim/rtl_sim/
2 Initial official release. mohor 8339d 04h /dbg_interface/tags/rel_7/sim/rtl_sim/

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