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[/] [dbg_interface/] [tags/] [rel_8/] - Rev 20

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20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8262d 12h /dbg_interface/tags/rel_8/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8274d 12h /dbg_interface/tags/rel_8/
18 Reset signals are not combined any more. mohor 8276d 21h /dbg_interface/tags/rel_8/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8300d 11h /dbg_interface/tags/rel_8/
16 bs_chain_o port added. mohor 8302d 11h /dbg_interface/tags/rel_8/
15 bs_chain_o added. mohor 8302d 12h /dbg_interface/tags/rel_8/
14 Document updated. mohor 8303d 09h /dbg_interface/tags/rel_8/
13 Signal names changed to lowercase. mohor 8303d 12h /dbg_interface/tags/rel_8/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8304d 13h /dbg_interface/tags/rel_8/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8325d 08h /dbg_interface/tags/rel_8/
10 First official release 1.0. mohor 8329d 12h /dbg_interface/tags/rel_8/
9 Working version. Few bugs fixed, comments added. mohor 8329d 12h /dbg_interface/tags/rel_8/
8 Asynchronous set/reset not used in trace any more. mohor 8330d 11h /dbg_interface/tags/rel_8/
7 First official release 1.0. mohor 8330d 11h /dbg_interface/tags/rel_8/
6 Minor changes for simulation. mohor 8330d 11h /dbg_interface/tags/rel_8/
5 Trace fixed. Some registers changed, trace simplified. mohor 8331d 08h /dbg_interface/tags/rel_8/
4 Initial official release. mohor 8336d 08h /dbg_interface/tags/rel_8/
2 Initial official release. mohor 8336d 09h /dbg_interface/tags/rel_8/
1 Standard project directories initialized by cvs2svn. 8336d 09h /dbg_interface/tags/rel_8/

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