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[/] [dbg_interface/] [tags/] [rel_8/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5562d 18h /dbg_interface/tags/rel_8/rtl/verilog/
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7563d 00h /dbg_interface/tags/rel_8/rtl/verilog/
67 Lower two address lines must be always zero. simons 7563d 00h /dbg_interface/tags/rel_8/rtl/verilog/
65 WB_CNTL register added, some syncronization fixes. simons 7564d 00h /dbg_interface/tags/rel_8/rtl/verilog/
63 Three more chains added for cpu debug access. simons 7584d 00h /dbg_interface/tags/rel_8/rtl/verilog/
61 Lapsus fixed. simons 7612d 00h /dbg_interface/tags/rel_8/rtl/verilog/
59 Reset value for riscsel register set to 1. simons 7612d 00h /dbg_interface/tags/rel_8/rtl/verilog/
57 Multiple cpu support added. simons 7612d 02h /dbg_interface/tags/rel_8/rtl/verilog/
53 Trst active high. Inverted on higher layer. mohor 7879d 00h /dbg_interface/tags/rel_8/rtl/verilog/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7879d 00h /dbg_interface/tags/rel_8/rtl/verilog/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7906d 11h /dbg_interface/tags/rel_8/rtl/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8061d 23h /dbg_interface/tags/rel_8/rtl/verilog/
46 Asynchronous reset used instead of synchronous. mohor 8070d 05h /dbg_interface/tags/rel_8/rtl/verilog/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8077d 01h /dbg_interface/tags/rel_8/rtl/verilog/
44 Signal names changed to lower case. mohor 8077d 01h /dbg_interface/tags/rel_8/rtl/verilog/
43 Intentional error removed. mohor 8082d 01h /dbg_interface/tags/rel_8/rtl/verilog/
42 A block for checking possible simulation/synthesis missmatch added. mohor 8082d 03h /dbg_interface/tags/rel_8/rtl/verilog/
41 Function changed to logic because of some synthesis warnings. mohor 8090d 00h /dbg_interface/tags/rel_8/rtl/verilog/
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8104d 00h /dbg_interface/tags/rel_8/rtl/verilog/
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8105d 01h /dbg_interface/tags/rel_8/rtl/verilog/

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