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[/] [dbg_interface/] [tags/] [rel_8/] [sim/] [rtl_sim/] - Rev 36

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Rev Log message Author Age Path
36 Structure changed. Hooks for jtag chain added. mohor 8153d 23h /dbg_interface/tags/rel_8/sim/rtl_sim/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8294d 03h /dbg_interface/tags/rel_8/sim/rtl_sim/
5 Trace fixed. Some registers changed, trace simplified. mohor 8325d 01h /dbg_interface/tags/rel_8/sim/rtl_sim/
2 Initial official release. mohor 8330d 01h /dbg_interface/tags/rel_8/sim/rtl_sim/

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