URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_9/] [sim/] [rtl_sim/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5571d 07h	/dbg_interface/tags/rel_9/sim/rtl_sim/
72	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7538d 17h	/dbg_interface/tags/rel_9/sim/rtl_sim/
36	Structure changed. Hooks for jtag chain added.	mohor	8130d 12h	/dbg_interface/tags/rel_9/sim/rtl_sim/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8270d 15h	/dbg_interface/tags/rel_9/sim/rtl_sim/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8301d 13h	/dbg_interface/tags/rel_9/sim/rtl_sim/
2	Initial official release.	mohor	8306d 13h	/dbg_interface/tags/rel_9/sim/rtl_sim/