OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rev_23/] - Rev 121

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7458d 00h /dbg_interface/tags/rev_23/
120 test stall_test added. mohor 7458d 03h /dbg_interface/tags/rev_23/
119 cpu_stall_o activated as soon as bp occurs. mohor 7458d 03h /dbg_interface/tags/rev_23/
117 Define name changed. mohor 7459d 23h /dbg_interface/tags/rev_23/
116 Data latching changed when testing WB. mohor 7460d 00h /dbg_interface/tags/rev_23/
115 More debug data added. mohor 7460d 03h /dbg_interface/tags/rev_23/
114 CRC generation iand verification in bench changed. mohor 7460d 05h /dbg_interface/tags/rev_23/
113 IDCODE test improved. mohor 7460d 06h /dbg_interface/tags/rev_23/
112 dbg_tb_defines.v not used. mohor 7461d 00h /dbg_interface/tags/rev_23/
111 Define tap_defines.v added to test bench. mohor 7461d 00h /dbg_interface/tags/rev_23/
110 Waiting for "ready" improved. mohor 7461d 01h /dbg_interface/tags/rev_23/
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7461d 06h /dbg_interface/tags/rev_23/
106 Sensitivity list updated. simons 7462d 04h /dbg_interface/tags/rev_23/
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7462d 19h /dbg_interface/tags/rev_23/
102 New version. mohor 7462d 20h /dbg_interface/tags/rev_23/
101 Almost finished. mohor 7462d 21h /dbg_interface/tags/rev_23/
100 *** empty log message *** mohor 7463d 23h /dbg_interface/tags/rev_23/
99 cpu registers added. mohor 7463d 23h /dbg_interface/tags/rev_23/
97 Working. mohor 7465d 02h /dbg_interface/tags/rev_23/
96 Working. mohor 7465d 03h /dbg_interface/tags/rev_23/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.