OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] - Rev 33

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8177d 16h /dbg_interface/tags/sdram_test_working/
32 Stupid bug that was entered by previous update fixed. mohor 8178d 15h /dbg_interface/tags/sdram_test_working/
31 trst synchronization is not needed and was removed. mohor 8178d 16h /dbg_interface/tags/sdram_test_working/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.
mohor 8189d 21h /dbg_interface/tags/sdram_test_working/
29 Document revised and put tp better form. mohor 8193d 10h /dbg_interface/tags/sdram_test_working/
28 TDO and TDO Enable signal are separated into two signals. mohor 8225d 17h /dbg_interface/tags/sdram_test_working/
27 Warnings from synthesys tools fixed. mohor 8239d 19h /dbg_interface/tags/sdram_test_working/
26 Warnings from synthesys tools fixed. mohor 8239d 19h /dbg_interface/tags/sdram_test_working/
25 trst signal is synchronized to wb_clk_i. mohor 8240d 15h /dbg_interface/tags/sdram_test_working/
24 CRC changed so more thorough testing is done. mohor 8241d 17h /dbg_interface/tags/sdram_test_working/
23 Trace disabled by default. mohor 8247d 19h /dbg_interface/tags/sdram_test_working/
22 Register length fixed. mohor 8247d 19h /dbg_interface/tags/sdram_test_working/
21 CRC is returned when chain selection data is transmitted. mohor 8248d 15h /dbg_interface/tags/sdram_test_working/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8249d 18h /dbg_interface/tags/sdram_test_working/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8261d 18h /dbg_interface/tags/sdram_test_working/
18 Reset signals are not combined any more. mohor 8264d 03h /dbg_interface/tags/sdram_test_working/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8287d 17h /dbg_interface/tags/sdram_test_working/
16 bs_chain_o port added. mohor 8289d 17h /dbg_interface/tags/sdram_test_working/
15 bs_chain_o added. mohor 8289d 18h /dbg_interface/tags/sdram_test_working/
14 Document updated. mohor 8290d 16h /dbg_interface/tags/sdram_test_working/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.