URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [bench/] [verilog/] - Rev 12

Rev	Log message	Author	Age	Path
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8330d 13h	/dbg_interface/tags/sdram_test_working/bench/verilog/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8351d 09h	/dbg_interface/tags/sdram_test_working/bench/verilog/
9	Working version. Few bugs fixed, comments added.	mohor	8355d 13h	/dbg_interface/tags/sdram_test_working/bench/verilog/
6	Minor changes for simulation.	mohor	8356d 11h	/dbg_interface/tags/sdram_test_working/bench/verilog/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8357d 09h	/dbg_interface/tags/sdram_test_working/bench/verilog/
2	Initial official release.	mohor	8362d 09h	/dbg_interface/tags/sdram_test_working/bench/verilog/