OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 TDO and TDO Enable signal are separated into two signals. mohor 8221d 06h /dbg_interface/tags/sdram_test_working/rtl/
27 Warnings from synthesys tools fixed. mohor 8235d 07h /dbg_interface/tags/sdram_test_working/rtl/
26 Warnings from synthesys tools fixed. mohor 8235d 07h /dbg_interface/tags/sdram_test_working/rtl/
25 trst signal is synchronized to wb_clk_i. mohor 8236d 03h /dbg_interface/tags/sdram_test_working/rtl/
23 Trace disabled by default. mohor 8243d 07h /dbg_interface/tags/sdram_test_working/rtl/
22 Register length fixed. mohor 8243d 07h /dbg_interface/tags/sdram_test_working/rtl/
21 CRC is returned when chain selection data is transmitted. mohor 8244d 03h /dbg_interface/tags/sdram_test_working/rtl/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8245d 06h /dbg_interface/tags/sdram_test_working/rtl/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8257d 07h /dbg_interface/tags/sdram_test_working/rtl/
18 Reset signals are not combined any more. mohor 8259d 16h /dbg_interface/tags/sdram_test_working/rtl/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8283d 05h /dbg_interface/tags/sdram_test_working/rtl/
15 bs_chain_o added. mohor 8285d 06h /dbg_interface/tags/sdram_test_working/rtl/
13 Signal names changed to lowercase. mohor 8286d 07h /dbg_interface/tags/sdram_test_working/rtl/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8287d 07h /dbg_interface/tags/sdram_test_working/rtl/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8308d 03h /dbg_interface/tags/sdram_test_working/rtl/
9 Working version. Few bugs fixed, comments added. mohor 8312d 07h /dbg_interface/tags/sdram_test_working/rtl/
8 Asynchronous set/reset not used in trace any more. mohor 8313d 05h /dbg_interface/tags/sdram_test_working/rtl/
5 Trace fixed. Some registers changed, trace simplified. mohor 8314d 03h /dbg_interface/tags/sdram_test_working/rtl/
2 Initial official release. mohor 8319d 03h /dbg_interface/tags/sdram_test_working/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.