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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] - Rev 20

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Rev Log message Author Age Path
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8250d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8262d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
18 Reset signals are not combined any more. mohor 8264d 11h /dbg_interface/tags/sdram_test_working/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8288d 01h /dbg_interface/tags/sdram_test_working/rtl/verilog/
15 bs_chain_o added. mohor 8290d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
13 Signal names changed to lowercase. mohor 8291d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8292d 03h /dbg_interface/tags/sdram_test_working/rtl/verilog/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8312d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/
9 Working version. Few bugs fixed, comments added. mohor 8317d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
8 Asynchronous set/reset not used in trace any more. mohor 8318d 01h /dbg_interface/tags/sdram_test_working/rtl/verilog/
5 Trace fixed. Some registers changed, trace simplified. mohor 8318d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/
2 Initial official release. mohor 8323d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/

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