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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] - Rev 37

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37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8144d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8147d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8178d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
32 Stupid bug that was entered by previous update fixed. mohor 8179d 01h /dbg_interface/tags/sdram_test_working/rtl/verilog/
31 trst synchronization is not needed and was removed. mohor 8179d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8190d 06h /dbg_interface/tags/sdram_test_working/rtl/verilog/
28 TDO and TDO Enable signal are separated into two signals. mohor 8226d 03h /dbg_interface/tags/sdram_test_working/rtl/verilog/
27 Warnings from synthesys tools fixed. mohor 8240d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
26 Warnings from synthesys tools fixed. mohor 8240d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
25 trst signal is synchronized to wb_clk_i. mohor 8241d 01h /dbg_interface/tags/sdram_test_working/rtl/verilog/
23 Trace disabled by default. mohor 8248d 05h /dbg_interface/tags/sdram_test_working/rtl/verilog/
22 Register length fixed. mohor 8248d 05h /dbg_interface/tags/sdram_test_working/rtl/verilog/
21 CRC is returned when chain selection data is transmitted. mohor 8249d 01h /dbg_interface/tags/sdram_test_working/rtl/verilog/
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8250d 03h /dbg_interface/tags/sdram_test_working/rtl/verilog/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8262d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
18 Reset signals are not combined any more. mohor 8264d 13h /dbg_interface/tags/sdram_test_working/rtl/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8288d 03h /dbg_interface/tags/sdram_test_working/rtl/verilog/
15 bs_chain_o added. mohor 8290d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
13 Signal names changed to lowercase. mohor 8291d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8292d 04h /dbg_interface/tags/sdram_test_working/rtl/verilog/

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