URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [sim/] [rtl_sim/] [run/] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5588d 00h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8087d 05h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/
36	Structure changed. Hooks for jtag chain added.	mohor	8147d 04h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8287d 08h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8318d 05h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/
2	Initial official release.	mohor	8323d 06h	/dbg_interface/tags/sdram_test_working/sim/rtl_sim/run/