URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] - Rev 140

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Rev	Log message	Author	Age	Path
140	CRC checking of incoming CRC added to all tasks.	igorm	7499d 00h	/dbg_interface/trunk/
139	New release of the debug interface (3rd. release).	igorm	7501d 03h	/dbg_interface/trunk/
138	Temp version before changing dbg interface.	igorm	7507d 07h	/dbg_interface/trunk/
136	Table describing chain codes added.	igorm	7511d 08h	/dbg_interface/trunk/
135	'hz changed to 1'hz because Icarus complains.	igorm	7514d 07h	/dbg_interface/trunk/
132	Documentation updated. Many missing things added.	igorm	7515d 06h	/dbg_interface/trunk/
131	Documentation updated. Many missing things added.	igorm	7515d 07h	/dbg_interface/trunk/
129	New documentation.	mohor	7557d 05h	/dbg_interface/trunk/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7559d 13h	/dbg_interface/trunk/
126	run_sim.scr renamed to run_sim for VATS.	mohor	7562d 13h	/dbg_interface/trunk/
124	Display for VATS added.	mohor	7564d 09h	/dbg_interface/trunk/
123	All flipflops are reset.	mohor	7564d 10h	/dbg_interface/trunk/
121	Port signals are all set to zero after reset.	mohor	7567d 10h	/dbg_interface/trunk/
120	test stall_test added.	mohor	7567d 13h	/dbg_interface/trunk/
119	cpu_stall_o activated as soon as bp occurs.	mohor	7567d 13h	/dbg_interface/trunk/
117	Define name changed.	mohor	7569d 09h	/dbg_interface/trunk/
116	Data latching changed when testing WB.	mohor	7569d 10h	/dbg_interface/trunk/
115	More debug data added.	mohor	7569d 13h	/dbg_interface/trunk/
114	CRC generation iand verification in bench changed.	mohor	7569d 14h	/dbg_interface/trunk/
113	IDCODE test improved.	mohor	7569d 16h	/dbg_interface/trunk/

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[/] [dbg_interface/] [trunk/] - Rev 140

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