URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] - Rev 111

Rev	Log message	Author	Age	Path
111	Define tap_defines.v added to test bench.	mohor	7500d 08h	/dbg_interface/trunk/bench/
110	Waiting for "ready" improved.	mohor	7500d 09h	/dbg_interface/trunk/bench/
102	New version.	mohor	7502d 03h	/dbg_interface/trunk/bench/
101	Almost finished.	mohor	7502d 04h	/dbg_interface/trunk/bench/
99	cpu registers added.	mohor	7503d 07h	/dbg_interface/trunk/bench/
96	Working.	mohor	7504d 11h	/dbg_interface/trunk/bench/
95	Temp version.	mohor	7504d 22h	/dbg_interface/trunk/bench/
93	tmp version.	mohor	7506d 10h	/dbg_interface/trunk/bench/
92	temp version.	mohor	7509d 14h	/dbg_interface/trunk/bench/
91	tmp version.	mohor	7510d 09h	/dbg_interface/trunk/bench/
90	tmp version.	mohor	7511d 03h	/dbg_interface/trunk/bench/
89	temp4 version.	mohor	7512d 09h	/dbg_interface/trunk/bench/
88	temp3 version.	mohor	7513d 04h	/dbg_interface/trunk/bench/
87	tmp2 version.	mohor	7514d 09h	/dbg_interface/trunk/bench/
80	New version of the debug interface. Not finished, yet.	mohor	7527d 07h	/dbg_interface/trunk/bench/
75	Simulation files.	mohor	7588d 05h	/dbg_interface/trunk/bench/
73	CRC logic changed.	mohor	7588d 05h	/dbg_interface/trunk/bench/
63	Three more chains added for cpu debug access.	simons	7644d 07h	/dbg_interface/trunk/bench/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8122d 07h	/dbg_interface/trunk/bench/
38	Few outputs for boundary scan chain added.	mohor	8178d 07h	/dbg_interface/trunk/bench/