URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] - Rev 140

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Rev	Log message	Author	Age	Path
140	CRC checking of incoming CRC added to all tasks.	igorm	7428d 20h	/dbg_interface/trunk/bench/
139	New release of the debug interface (3rd. release).	igorm	7430d 23h	/dbg_interface/trunk/bench/
138	Temp version before changing dbg interface.	igorm	7437d 03h	/dbg_interface/trunk/bench/
135	'hz changed to 1'hz because Icarus complains.	igorm	7444d 03h	/dbg_interface/trunk/bench/
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7489d 09h	/dbg_interface/trunk/bench/
124	Display for VATS added.	mohor	7494d 05h	/dbg_interface/trunk/bench/
121	Port signals are all set to zero after reset.	mohor	7497d 05h	/dbg_interface/trunk/bench/
120	test stall_test added.	mohor	7497d 08h	/dbg_interface/trunk/bench/
117	Define name changed.	mohor	7499d 05h	/dbg_interface/trunk/bench/
116	Data latching changed when testing WB.	mohor	7499d 05h	/dbg_interface/trunk/bench/
115	More debug data added.	mohor	7499d 09h	/dbg_interface/trunk/bench/
114	CRC generation iand verification in bench changed.	mohor	7499d 10h	/dbg_interface/trunk/bench/
113	IDCODE test improved.	mohor	7499d 11h	/dbg_interface/trunk/bench/
112	dbg_tb_defines.v not used.	mohor	7500d 06h	/dbg_interface/trunk/bench/
111	Define tap_defines.v added to test bench.	mohor	7500d 06h	/dbg_interface/trunk/bench/
110	Waiting for "ready" improved.	mohor	7500d 07h	/dbg_interface/trunk/bench/
102	New version.	mohor	7502d 01h	/dbg_interface/trunk/bench/
101	Almost finished.	mohor	7502d 02h	/dbg_interface/trunk/bench/
99	cpu registers added.	mohor	7503d 05h	/dbg_interface/trunk/bench/
96	Working.	mohor	7504d 09h	/dbg_interface/trunk/bench/

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] - Rev 140

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