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[/] [dbg_interface/] [trunk/] [bench/] - Rev 93

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Rev Log message Author Age Path
93 tmp version. mohor 7506d 23h /dbg_interface/trunk/bench/
92 temp version. mohor 7510d 03h /dbg_interface/trunk/bench/
91 tmp version. mohor 7510d 22h /dbg_interface/trunk/bench/
90 tmp version. mohor 7511d 17h /dbg_interface/trunk/bench/
89 temp4 version. mohor 7512d 22h /dbg_interface/trunk/bench/
88 temp3 version. mohor 7513d 17h /dbg_interface/trunk/bench/
87 tmp2 version. mohor 7514d 22h /dbg_interface/trunk/bench/
80 New version of the debug interface. Not finished, yet. mohor 7527d 20h /dbg_interface/trunk/bench/
75 Simulation files. mohor 7588d 18h /dbg_interface/trunk/bench/
73 CRC logic changed. mohor 7588d 18h /dbg_interface/trunk/bench/
63 Three more chains added for cpu debug access. simons 7644d 21h /dbg_interface/trunk/bench/
47 mon_cntl_o signals that controls monitor mux added. mohor 8122d 20h /dbg_interface/trunk/bench/
38 Few outputs for boundary scan chain added. mohor 8178d 20h /dbg_interface/trunk/bench/
36 Structure changed. Hooks for jtag chain added. mohor 8182d 19h /dbg_interface/trunk/bench/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8322d 23h /dbg_interface/trunk/bench/
15 bs_chain_o added. mohor 8325d 00h /dbg_interface/trunk/bench/
13 Signal names changed to lowercase. mohor 8326d 00h /dbg_interface/trunk/bench/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8327d 01h /dbg_interface/trunk/bench/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8347d 20h /dbg_interface/trunk/bench/
9 Working version. Few bugs fixed, comments added. mohor 8352d 00h /dbg_interface/trunk/bench/

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