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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 101

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Rev Log message Author Age Path
101 Almost finished. mohor 7515d 14h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7516d 16h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7517d 20h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7518d 08h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7519d 19h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7522d 23h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7523d 18h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7524d 13h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7525d 19h /dbg_interface/trunk/bench/verilog/
88 temp3 version. mohor 7526d 13h /dbg_interface/trunk/bench/verilog/
87 tmp2 version. mohor 7527d 18h /dbg_interface/trunk/bench/verilog/
80 New version of the debug interface. Not finished, yet. mohor 7540d 16h /dbg_interface/trunk/bench/verilog/
75 Simulation files. mohor 7601d 14h /dbg_interface/trunk/bench/verilog/
73 CRC logic changed. mohor 7601d 14h /dbg_interface/trunk/bench/verilog/
63 Three more chains added for cpu debug access. simons 7657d 17h /dbg_interface/trunk/bench/verilog/
47 mon_cntl_o signals that controls monitor mux added. mohor 8135d 16h /dbg_interface/trunk/bench/verilog/
38 Few outputs for boundary scan chain added. mohor 8191d 16h /dbg_interface/trunk/bench/verilog/
36 Structure changed. Hooks for jtag chain added. mohor 8195d 15h /dbg_interface/trunk/bench/verilog/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8335d 19h /dbg_interface/trunk/bench/verilog/
15 bs_chain_o added. mohor 8337d 20h /dbg_interface/trunk/bench/verilog/

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