URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 113

Rev	Log message	Author	Age	Path
113	IDCODE test improved.	mohor	7475d 16h	/dbg_interface/trunk/bench/verilog/
112	dbg_tb_defines.v not used.	mohor	7476d 11h	/dbg_interface/trunk/bench/verilog/
111	Define tap_defines.v added to test bench.	mohor	7476d 11h	/dbg_interface/trunk/bench/verilog/
110	Waiting for "ready" improved.	mohor	7476d 11h	/dbg_interface/trunk/bench/verilog/
102	New version.	mohor	7478d 06h	/dbg_interface/trunk/bench/verilog/
101	Almost finished.	mohor	7478d 07h	/dbg_interface/trunk/bench/verilog/
99	cpu registers added.	mohor	7479d 09h	/dbg_interface/trunk/bench/verilog/
96	Working.	mohor	7480d 13h	/dbg_interface/trunk/bench/verilog/
95	Temp version.	mohor	7481d 01h	/dbg_interface/trunk/bench/verilog/
93	tmp version.	mohor	7482d 13h	/dbg_interface/trunk/bench/verilog/
92	temp version.	mohor	7485d 16h	/dbg_interface/trunk/bench/verilog/
91	tmp version.	mohor	7486d 11h	/dbg_interface/trunk/bench/verilog/
90	tmp version.	mohor	7487d 06h	/dbg_interface/trunk/bench/verilog/
89	temp4 version.	mohor	7488d 12h	/dbg_interface/trunk/bench/verilog/
88	temp3 version.	mohor	7489d 07h	/dbg_interface/trunk/bench/verilog/
87	tmp2 version.	mohor	7490d 12h	/dbg_interface/trunk/bench/verilog/
80	New version of the debug interface. Not finished, yet.	mohor	7503d 10h	/dbg_interface/trunk/bench/verilog/
75	Simulation files.	mohor	7564d 08h	/dbg_interface/trunk/bench/verilog/
73	CRC logic changed.	mohor	7564d 08h	/dbg_interface/trunk/bench/verilog/
63	Three more chains added for cpu debug access.	simons	7620d 10h	/dbg_interface/trunk/bench/verilog/