URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 116

Rev	Log message	Author	Age	Path
116	Data latching changed when testing WB.	mohor	7499d 09h	/dbg_interface/trunk/bench/verilog/
115	More debug data added.	mohor	7499d 13h	/dbg_interface/trunk/bench/verilog/
114	CRC generation iand verification in bench changed.	mohor	7499d 14h	/dbg_interface/trunk/bench/verilog/
113	IDCODE test improved.	mohor	7499d 15h	/dbg_interface/trunk/bench/verilog/
112	dbg_tb_defines.v not used.	mohor	7500d 10h	/dbg_interface/trunk/bench/verilog/
111	Define tap_defines.v added to test bench.	mohor	7500d 10h	/dbg_interface/trunk/bench/verilog/
110	Waiting for "ready" improved.	mohor	7500d 10h	/dbg_interface/trunk/bench/verilog/
102	New version.	mohor	7502d 05h	/dbg_interface/trunk/bench/verilog/
101	Almost finished.	mohor	7502d 06h	/dbg_interface/trunk/bench/verilog/
99	cpu registers added.	mohor	7503d 08h	/dbg_interface/trunk/bench/verilog/
96	Working.	mohor	7504d 12h	/dbg_interface/trunk/bench/verilog/
95	Temp version.	mohor	7505d 00h	/dbg_interface/trunk/bench/verilog/
93	tmp version.	mohor	7506d 12h	/dbg_interface/trunk/bench/verilog/
92	temp version.	mohor	7509d 15h	/dbg_interface/trunk/bench/verilog/
91	tmp version.	mohor	7510d 10h	/dbg_interface/trunk/bench/verilog/
90	tmp version.	mohor	7511d 05h	/dbg_interface/trunk/bench/verilog/
89	temp4 version.	mohor	7512d 11h	/dbg_interface/trunk/bench/verilog/
88	temp3 version.	mohor	7513d 06h	/dbg_interface/trunk/bench/verilog/
87	tmp2 version.	mohor	7514d 11h	/dbg_interface/trunk/bench/verilog/
80	New version of the debug interface. Not finished, yet.	mohor	7527d 09h	/dbg_interface/trunk/bench/verilog/