OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 121

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7462d 22h /dbg_interface/trunk/bench/verilog/
120 test stall_test added. mohor 7463d 01h /dbg_interface/trunk/bench/verilog/
117 Define name changed. mohor 7464d 22h /dbg_interface/trunk/bench/verilog/
116 Data latching changed when testing WB. mohor 7464d 22h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7465d 02h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7465d 03h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7465d 04h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7465d 23h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7465d 23h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7466d 00h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7467d 18h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7467d 19h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7468d 21h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7470d 01h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7470d 13h /dbg_interface/trunk/bench/verilog/
93 tmp version. mohor 7472d 01h /dbg_interface/trunk/bench/verilog/
92 temp version. mohor 7475d 04h /dbg_interface/trunk/bench/verilog/
91 tmp version. mohor 7475d 23h /dbg_interface/trunk/bench/verilog/
90 tmp version. mohor 7476d 18h /dbg_interface/trunk/bench/verilog/
89 temp4 version. mohor 7478d 00h /dbg_interface/trunk/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.