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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 139

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Rev Log message Author Age Path
139 New release of the debug interface (3rd. release). igorm 7396d 16h /dbg_interface/trunk/bench/verilog/
138 Temp version before changing dbg interface. igorm 7402d 20h /dbg_interface/trunk/bench/verilog/
135 'hz changed to 1'hz because Icarus complains. igorm 7409d 20h /dbg_interface/trunk/bench/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7455d 02h /dbg_interface/trunk/bench/verilog/
124 Display for VATS added. mohor 7459d 23h /dbg_interface/trunk/bench/verilog/
121 Port signals are all set to zero after reset. mohor 7462d 23h /dbg_interface/trunk/bench/verilog/
120 test stall_test added. mohor 7463d 02h /dbg_interface/trunk/bench/verilog/
117 Define name changed. mohor 7464d 22h /dbg_interface/trunk/bench/verilog/
116 Data latching changed when testing WB. mohor 7464d 23h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7465d 02h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7465d 04h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7465d 05h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7465d 23h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7466d 00h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7466d 00h /dbg_interface/trunk/bench/verilog/
102 New version. mohor 7467d 19h /dbg_interface/trunk/bench/verilog/
101 Almost finished. mohor 7467d 20h /dbg_interface/trunk/bench/verilog/
99 cpu registers added. mohor 7468d 22h /dbg_interface/trunk/bench/verilog/
96 Working. mohor 7470d 02h /dbg_interface/trunk/bench/verilog/
95 Temp version. mohor 7470d 14h /dbg_interface/trunk/bench/verilog/

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