OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5584d 10h /dbg_interface/trunk/bench/verilog/
145 Support for 2 CPUs added. igorm 7388d 17h /dbg_interface/trunk/bench/verilog/
142 Typo fixed. igorm 7388d 21h /dbg_interface/trunk/bench/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7389d 16h /dbg_interface/trunk/bench/verilog/
140 CRC checking of incoming CRC added to all tasks. igorm 7390d 07h /dbg_interface/trunk/bench/verilog/
139 New release of the debug interface (3rd. release). igorm 7392d 10h /dbg_interface/trunk/bench/verilog/
138 Temp version before changing dbg interface. igorm 7398d 14h /dbg_interface/trunk/bench/verilog/
135 'hz changed to 1'hz because Icarus complains. igorm 7405d 14h /dbg_interface/trunk/bench/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7450d 20h /dbg_interface/trunk/bench/verilog/
124 Display for VATS added. mohor 7455d 16h /dbg_interface/trunk/bench/verilog/
121 Port signals are all set to zero after reset. mohor 7458d 16h /dbg_interface/trunk/bench/verilog/
120 test stall_test added. mohor 7458d 19h /dbg_interface/trunk/bench/verilog/
117 Define name changed. mohor 7460d 16h /dbg_interface/trunk/bench/verilog/
116 Data latching changed when testing WB. mohor 7460d 16h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7460d 20h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7460d 21h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7460d 22h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7461d 17h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7461d 17h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7461d 18h /dbg_interface/trunk/bench/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.