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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5580d 22h /dbg_interface/trunk/bench/verilog/
145 Support for 2 CPUs added. igorm 7385d 05h /dbg_interface/trunk/bench/verilog/
142 Typo fixed. igorm 7385d 08h /dbg_interface/trunk/bench/verilog/
141 data_cnt_lim length changed to reduce number of warnings. igorm 7386d 03h /dbg_interface/trunk/bench/verilog/
140 CRC checking of incoming CRC added to all tasks. igorm 7386d 19h /dbg_interface/trunk/bench/verilog/
139 New release of the debug interface (3rd. release). igorm 7388d 21h /dbg_interface/trunk/bench/verilog/
138 Temp version before changing dbg interface. igorm 7395d 01h /dbg_interface/trunk/bench/verilog/
135 'hz changed to 1'hz because Icarus complains. igorm 7402d 02h /dbg_interface/trunk/bench/verilog/
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7447d 07h /dbg_interface/trunk/bench/verilog/
124 Display for VATS added. mohor 7452d 04h /dbg_interface/trunk/bench/verilog/
121 Port signals are all set to zero after reset. mohor 7455d 04h /dbg_interface/trunk/bench/verilog/
120 test stall_test added. mohor 7455d 07h /dbg_interface/trunk/bench/verilog/
117 Define name changed. mohor 7457d 03h /dbg_interface/trunk/bench/verilog/
116 Data latching changed when testing WB. mohor 7457d 04h /dbg_interface/trunk/bench/verilog/
115 More debug data added. mohor 7457d 07h /dbg_interface/trunk/bench/verilog/
114 CRC generation iand verification in bench changed. mohor 7457d 09h /dbg_interface/trunk/bench/verilog/
113 IDCODE test improved. mohor 7457d 10h /dbg_interface/trunk/bench/verilog/
112 dbg_tb_defines.v not used. mohor 7458d 04h /dbg_interface/trunk/bench/verilog/
111 Define tap_defines.v added to test bench. mohor 7458d 05h /dbg_interface/trunk/bench/verilog/
110 Waiting for "ready" improved. mohor 7458d 05h /dbg_interface/trunk/bench/verilog/

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